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Sonics Integrates Smart Interconnect IP with Cadence and CoWare Electronic System-Level -- ESL -- Design-for-Verification Flow
Rapid Interactive Design Flow Now Possible at Every Stage
of System-Level Design, Co-Simulation, Verification,
Hardware Integration and Implementation
MOUNTAIN VIEW, Calif.—(BUSINESS WIRE)—June 28, 2004—
Sonics, Inc., a leading provider of SoC (system-on-chip)
architectures and SMART Interconnect IP products that reduce the time,
cost and risk of developing complex SoC devices, announced today that
the company has joined Cadence Design Systems, Inc. (NYSE:CDN) and
CoWare, Inc. in supporting the Cadence/CoWare integrated, seamless
flow for electronic system-level (ESL) design through verification for
complex SoC designs.
The flow is based on tight integration between CoWare's
SystemC-based ConvergenSC(TM) SoC design tools, the ConvergenSC Model
Library and the Cadence Incisive(TM) functional verification platform.
Into this flow, Sonics adds its SMART Interconnect IP(TM) that
integrates multiple IP blocks into working silicon and its
SonicsStudio(TM) interconnect IP configuration tool. This completes
the concept-to-silicon vision with tight integration to a wide array
of hardware IP.
Time to verification and time to global timing closure are the two
issues delaying rapid development of complex SoCs. The CoWare/Cadence
ESL design flow reduces the time to verification by 50%. The addition
of Sonics IP reduces the time to global timing closure by 50%.
System Timing Closure
Today, critical timing paths within complex SoCs are not known
until the physical prototyping stage, when actual interconnect becomes
available. Only from this point can timing closure be addressed, often
resulting in complete architectural redesign. Using Sonics
Interconnect IP brings those physical timing constraints to the system
design level and, using SonicsStudio, injects them into the
Cadence/CoWare ESL flow.
The link between SonicsStudio and the Cadence/CoWare
design-to-verification flow is through the exchange of automatically
generated SystemC transaction level models of the entire SoC including
configured interconnects.
Sonics Closes Links to the Physical Domain
Further integrating the ESL flow to the physical domain, Sonics
has enabled the importation of LEF/DEF files from Cadence's
Encounter(TM) digital IC design platform. This enables the designer to
directly compare the floor plan connections with the physical
connections of the SMART Interconnect IP. This abstracted, but
physically accurate view of the SoC now gives the designer the ability
to find and correct architectural flaws in the first days or weeks of
design instead of the final months.
Sonics provides an essential link to the myriad of third party and
internally developed IP blocks that are needed to construct complex,
multimillion gate SoCs. Its SMART Interconnect IP connects complex IP
blocks such as microprocessors, DSPs, hardware accelerators such as
MPEG, DMA or packet processors with any other IP block with a high
degree of silicon efficiency and high data throughput.
"Our customers wanted a seamless flow from concept-to-silicon and
the new Cadence/CoWare initiative is an important milestone for the
industry," said Grant Pierce, president and CEO of Sonics, Inc. "Our
participation brings the advantage of a comprehensive, field-proven
SoC interconnect architecture to this flow. This builds on our
previously announced strategic partnerships with CoWare and Cadence.
Sonics completes the CoWare and Cadence ESL design flow with hardware
interconnect IP and SoC integration tools."
"We are pleased to see IP vendors such as Sonics supporting the
Cadence and CoWare ESL design-for-verification solution," said Mitch
Weaver, vice president and general manager, Systems and Functional
Verification Division, Cadence. "This is part of our overall plan to
encourage IP providers to join in this standards-based, SystemC-based
integrated solution."
"Our customers want a faster way to develop higher quality silicon
and having Sonics on board helps achieves this goal," said Alan
Naumann, president and CEO of CoWare. "Now our customers can easily
integrate our system-level ConvergenSC environment with Cadence's
tools and Sonics' SMART Interconnect IP to rapidly design
differentiated, multi-million gate SoCs."
Sonics and CoWare will streamline and optimize the
interoperability between Sonics SMART Interconnect IP, SonicsStudio
and CoWare's ConvergenSC platform. SonicsStudio is a comprehensive
suite of SoC integration, IP configuration, logic verification tools
and utilities. Users of SonicsStudio and ConvergenSC will now share
interoperable SystemC models and enjoy interoperability with the
largest SystemC model library.
"Now, customers of Sonics, CoWare and Cadence can rapidly interact
with their design at the ESL design level with confidence that their
architectural decisions will be reflected directly down to the
physical SoC integration level," said James Colgan, director of
marketing at Sonics, Inc.
About CoWare, Inc.
CoWare is the leading supplier of system-level electronic design
automation (EDA) software tools and services. CoWare offers a
comprehensive set of electronic system-level (ESL) tools that enable
SoC developers to "differentiate by design" through the creation of
system-IP including embedded processors, on-chip buses, and DSP
algorithms; the architecture of optimized SoC platforms; and
hardware/software co-design. The company's solutions are based on open
industry standards including SystemC. CoWare's customers are major
systems, semiconductor, and IP companies in the market where consumer
electronics, computing, and communications converge. CoWare's
corporate investors include ARM Ltd. ((LSE:ARM);(Nasdaq:ARMHY)),
Cadence Design Systems (NYSE:CDN), STMicroelectronics (NYSE:STM), and
Sony Corporation (NYSE:SNE). CoWare is headquartered in San Jose,
Calif., and has offices around the world. For more information about
CoWare and its products and services, visit www.coware.com.
About Sonics, Inc.
Sonics, Inc. is a leading provider of SoC architectures and SMART
Interconnect Intellectual Property (IP) that accelerate the
development of complex SoCs, reduce development costs and increase the
reusability of IP. Major semiconductor and systems companies including
Broadcom, Samsung, Texas Instruments and Toshiba have applied Sonics
architectures, IP products and methodologies in SoCs used in leading
products in the wireless, digital multimedia and communications
markets. Sonics customers have experienced dramatic reduction in time
to market, from years to months, while enjoying savings in design and
manufacturing costs. Sonics is a privately held company funded by
Investar Capital, Smart Technology Ventures, TL Ventures, Easton Hunt
Capital Partners, L.P, Globespan Capital Partners, and H&Q
Asia-Pacific. For more information, see www.sonicsinc.com.
SMART Interconnect IP and SonicsStudio are trademarks of Sonics,
Inc. Cadence is a registered trademark and Incisive is a trademark of
Cadence Design Systems, Inc. ConvergenSC is a trademark of CoWare,
Inc. All other trademarks are the property of their respective owners.
Contact:
Big Wave PR
Constance Sweeney, 650-358-9119
cks@bigwavepr.com
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